There is a type of photodetecting device which includes a photodiode that generates electric charge of an amount according to the intensity of incident light, an integrating circuit that accumulates an electric charge generated by the photodiode and outputs a voltage value according to the amount of the accumulated electric charge, and a CDS (Correlated Double Sampling) circuit for removing an offset error and a switching noise (hereinafter, both are collectively referred to as “an offset error etc.”) from the voltage value of the integrating circuit.
A configuration of a general photodetecting device including a CDS circuit is shown in FIG. 9. The photodetecting device 3 shown in this figure includes a photodiode PDx, a switch SWx for the photodiode, an integrating circuit 32, and a CDS circuit 33. The CDS circuit 33 includes a first voltage holding circuit 341, a second voltage holding circuit 342, and a differential conversion circuit 35. The differential conversion circuit 35 is composed of an amplifier and four resistors. In addition, as the differential conversion circuit, for example, one described in Non-Patent Document 1 can also be used.
An operation of the photodetecting device 3 shown in FIG. 9 will be explained. The operation to be explained in the following is performed under control of an unillustrated controlling section. FIG. 10 is a timing chart for explaining operation of the photodetecting device 3. In this figure, shown is (a) opening and closing of a reset switch SW7 included in the integrating circuit 32, (b) opening and closing of the switch SWx for photodiode provided along with the photodiode PDx, (c) opening and closing of a switch SW81 included in the first holding circuit 341, (d) opening and closing of the switch SW82 included in the second holding circuit 342, (e) an output voltage value from the integrating circuit 32, (f) an output voltage value from the first holding circuit 341, and (g) an output voltage value from the second holding circuit 342.
The respective times shown in FIG. 10 have an anteroposterior relationship of “t31<t32<t33<t34<t35<t36<t37.” For a period from time t32 to t35, the integrating circuit 32 is in a charge accumulable state because the reset switch SW7 is open, but an electric charge is never input from the photodiode PDx because the switch SWx for photodiode is open, and no electric charge is accumulated in a capacitor Cf of the integrating circuit 32. However, the output voltage value from the integrating circuit 32 monotonously changes after time t32 where the reset switch SW7 is turned from a closed state to an open state, and before long reaches an almost constant voltage value (that is, an offset voltage value) due to an offset error etc., at a certain time before time t33.
In the second holding circuit 342, when the switch SW82 closed at time t33 is opened at time t34, a voltage value according to the output voltage value of the integrating circuit 32 at time t34 is held by the second holding circuit 342, and after time t34, the held voltage value is output from the second holding circuit 342. The voltage value to be output indicates an offset voltage value that is output from the integrating circuit 32.
When the switch SWx for photodiode is closed for a certain period from time t35, an electric charge that has been generated by the photodiode PDx and accumulated in a junction capacitance section of the photodiode PDx is input to the integrating circuit 32 through the switch SWx for photodiode, and accumulated in the capacitor Cf of the integrating circuit 32. Therefore, the voltage value that is output from the integrating circuit 32 results in a superimposed value of a signal voltage value according to the amount of electric charge accumulated in the capacitor Cf and the offset voltage value.
In the first holding circuit 341, when the switch SW81 closed at time t36 is opened at time t37, a voltage value according to the output voltage value of the integrating circuit 32 at time t37 is held by the first holding circuit 341, and after time t37, the held voltage value is output from the first holding circuit 341. This voltage value indicates a signal voltage value superimposed with the offset voltage value that is output from the integrating circuit 32.
The voltage values output from the first holding circuit 341 and the second holding circuit 342 are input to the differential conversion circuit 35. In the differential conversion circuit 35, a voltage value according to a difference in these two voltage values is output as a differential signal. The voltage value to be output is to indicate a signal voltage value from which an offset error etc., has been removed. Non-Patent Document 1: TEXAS INSTRUMENTS Corp., ADS8482 data sheet, FIG. 8